1. Field of the Invention
The present invention relates to a data verification method operative within a semiconductor memory device. More particularly, the invention relates to a data verification method and semiconductor memory device for selectively verifying data written in a memory cell based on a data value.
2. Description of Related Art
Non-volatile memory devices capable of performing electrical erasing and programming operations may preserve data even when electrical power is interrupted. Flash memory is one representative example of contemporary non-volatile memory devices.
Each memory cell in a flash memory comprises a cell transistor including a control gate, a floating gate, a source, and a drain. The cell transistor is programmed or erased using an electrical charge transfer mechanism called Fowler-Nordheim (F-N) tunneling.
An erase operation for the cell transistor is performed by applying a ground voltage to the control gate and a voltage higher than the source voltage to the constituent semiconductor substrate or transistor bulk. Under this erase bias condition, a strong electric field is formed between the floating gate and bulk due to a large voltage difference between these two elements, thus electrons stored on the floating gate migrate to the bulk due to the F-N tunneling effect. In this case, the threshold voltage of the erased cell transistor is changed in a negative direction.
A program operation for the cell transistor is performed by applying a voltage higher than the source voltage to the control gate and applying ground voltage to the drain and bulk. Under this program bias condition, electrons are injected onto the floating gate of the cell transistor due to the F-N tunneling effect. In this case, the threshold voltage of the programmed cell transistor is changed in a positive direction.
FIG. 1 is a collection of related diagrams further illustrating the general structure and operation of a memory cell in a conventional non-volatile memory device.
Referring to FIG. 1, and continuing with the working example described above, electrons are accumulated on the floating gate FG of the memory cell during a program operation, and are removed from the floating gate FG during an erase operation. As a result, the threshold voltage of the memory cell transistor following a program operation is greater than 0V, but is less than 0V following an erase operation.
Recently, much research has been conducted in regard to multi-level flash memory in which a plurality of data bits (i.e., two or more) are stored in a single memory cell in order to improve integration of flash memory. A memory cell storing the multi-bit data is referred to as a multi-level cell. On the other hand, a memory cell storing a single bit data is referred to as a single-level cell. A multi-level cell stores multi-bit data using two or more threshold voltage distributions corresponding to two or more data storage states. A case where two-bit data is stored in the multi-level cell is illustrated in FIG. 2, wherein single bit data stored in a single-level cell is illustrated in FIG. 1. However, three or more bits of data may be stored in the multi-level cell.
A conventional multi-level cell storing the two-bit data is capable of being programmed into one of four data states which correspond to stored data values of 01, 10, and 00. The data state corresponding to a stored data value of 11 is commonly designated as an erase state, whereas the data states corresponding to 10, and 00 are programmed states.
Voltage levels associated with the four data states correspond to threshold voltage distributions for the multi-level cell. For example, assuming the threshold the data states 11, 01, 10, and 00 correspond to the threshold voltage distributions VTH1˜VTH2, VTH3˜VTH4, VTH5˜VTH6, and VTH7˜VTH8, respectively. That is, a threshold voltage of the multi-level cell corresponds to one of the threshold voltage distributions VTH1˜VTH2, VTH3˜VTH4, VTH5˜VTH6, and VTH7˜VTH8, and two-bit data corresponding to one of the data states 11, 01, 10, and 00 is stored in the multi-level cell.
The diagrams shown in FIG. 2 further illustrates the programming of multiple data states (1st through 4th) in relation to respective electron accumulations on a floating gate FG formed between a transistor bulk (e.g., a P+ substrate) and a control gate CG. N+ of FIG. 2 illustrates source or drain of a cell transistor. FIG. 3 is a related graph illustrating changes in threshold voltage distributions in relation to a multi-level cell.
Referring FIG. 2, an erase (or first) state is defined as one in which few (e.g., a practical minimum) electrons are accumulated on the floating gate FG of the multi-level cell. The various program states (second through fourth) are defined by progressively more electrons accumulated on the floating gate FG. As the quantity of charge accumulates on the floating gate FG, the threshold voltage of the multi-level cell increases. Thus, the threshold voltage distributions for the multi-level cell increase from the erase state through the various program states in accordance with the quantity of charge accumulated on the floating gate.
As is well understood in the art, once multi-bit data has been written to a multi-level cell, said data must be verified. That is, the actual threshold voltage of the multi-level cell is verified following a program operation to determine whether it is consistent with an intended data state.
In the example illustrated in FIG. 3, multi-bit data (e.g., 4-bit data) is stored in a multi-level cell and may be verified by using reference threshold voltage levels a1, a3, a5, a7, a9, a11, a13, a15, b1, b3, b5, b7, b9, b11, b13, and b15. These reference threshold voltage levels are disposed in relation to defined threshold voltage distributions for the multi-level cell and may be used to determine whether an actual threshold voltage is consistent with an intended data state. For example, if write data (i.e., data intended to be stored in a multi-level memory cell) is 0001, it must be determined whether the actual threshold voltage for the multi-level cell following the incident program operation is properly established between the reference threshold voltage levels a7 and b7.
However, in a conventional approach to programmed data verification, the threshold voltage of the multi-level cell must be sequentially compared to all of the reference threshold voltages. Thus, in the example illustrated in FIG. 3, the actual threshold voltage of the multi-level cell must be compared all sixteen (16) reference threshold voltage levels a1, a3, a5, a7, a9, a11, a13, a15, b1, b3, b5, b7, b9, b11, b13, and b15. Thus, as the number of data bits in the programmed data rises and the corresponding number of reference threshold voltages rises accordingly, the conventional approach to verifying an actual threshold voltage increases dramatically. At some point, depending on related memory system performance characteristics and requirements, this conventional approach will fail to operate sufficiently fast to allow effective data verification.